CORE REV: 5.0.0-PROD • MISRA-C/C++ ALIGNED • ZERO FPU REQUIRED
ARM CORTEX-M0+/M4/M7/M33 • ESP32 • HOST EVALUATION

Zero Heap, Sub-Millisecond Execution

Engineered for mission-critical industrial applications where memory corruption, watch-dog timer timeouts, and unhandled floating-point exceptions are unacceptable.

Parameter Value Design Basis & Verification Method
SRAM Consumption 375 Bytes Total 296 Bytes static .bss state machine + ~79 Bytes active stack frame. Zero heap growth.
Flash / ROM Consumption 1,712 Bytes Stripped static library object (.a). Compiles directly into your application firmware image.
Worst-Case Execution Time (WCET) 101.6 µs @ 240 MHz 24,396 hardware clock cycles. Consumes <0.2% CPU when evaluated at 15.6 Hz.
Arithmetic Unit 100% Fixed-Point Integer Zero FPU required. Pure 32/64-bit integer bit-shift and Newton-Raphson square root.
Dynamic Memory Allocation 0 Bytes (malloc = 0) MISRA Rule 21.3 compliant. Prevents runtime memory fragmentation and memory leaks.
Continuous Endurance Qualification 0.00000% False Alarm Rate Validated across 320,000,000 physical sensor samples (10M windows / 7.4 continuous days).
Defect Trip Latency 1.28 Seconds (20 windows) Decisive health decay latch upon real bearing raceway micro-spalling inception.
Sensor Ingestion Agility Sensor-Agnostic SPI / I2C Ingests standard 16/20/24-bit tri-axial integer counts directly from FIFO (Analog Devices, STMicro, Bosch, TDK).
Drive & Speed Compatibility VFD & Fixed Speed Dynamic baseline tracking supports inverter-driven variable speed motors (300 to 6,000+ RPM) with startup transient lockout.
ARM Cortex-M0+ (STM32G0/C0, RP2040) ARM Cortex-M4 (STM32F4/G4, TI, NXP) ARM Cortex-M7 (STM32H7, i.MX RT) ARM Cortex-M33 (STM32U5, nRF5340) Espressif ESP32 / ESP32-S3 x86_64 / Apple Silicon Host (SITL)
Analog Devices ADXL355 / ADXL357 / ADXL317 STMicroelectronics IIS3DWB / ISM330DHCX Bosch Sensortec BMA400 / BMI088 TDK InvenSense IIM-42352 / IIM-42652

3-Stage Autonomous Protection Architecture

Eliminates false alarms caused by plant floor noise, dropped tools, and motor startup speed ramping without compromising sub-second defect detection.

SAFEGUARD 01

Speed-Ramp Transient Gate

Monitors rotor acceleration during startup (0 to rated RPM). Discards startup inrush current shocks and torque transient spikes during the initial 1.28s window before establishing steady-state baseline tracking.

SAFEGUARD 02

Transient Outlier Shock Shield

Distinguishes between continuous structural bearing degradation and isolated mechanical shocks (e.g. dropped wrenches, pipe fluid hammer, or forklift base bumps). Single-sample outliers are filtered prior to health decay.

SAFEGUARD 03

Epistemic Anti-Poisoning Lock

Prevents model poisoning. When mechanical defect energy rises above nominal baseline thresholds, the adaptation gates instantly clamp to prevent the engine from learning anomalous vibration as "new normal."

Drop-In C-Linkage Interface

Integrates into existing FreeRTOS, Zephyr, or bare-metal motor control firmware in fewer than 10 lines of code. No hardware timers or peripherals are hijacked.

motor_sensor_task.c Standard ANSI C Header Integration
/* 1. Include the clean public header: */
#include "ac_engine.h"

void sensor_task_process_vibration(const int32_t *x_fifo, const int32_t *y_fifo, const int32_t *z_fifo) {
    /* 2. Feed 32 accelerometer counts into engine (execution: 101.6 µs): */
    ac_result_t result = ac_engine_feed_and_evaluate(x_fifo, y_fifo, z_fifo, 32);

    /* 3. Output to local HMI keypad screen or visual status LED: */
    lcd_set_health_display(result.health_index); /* Continuous: 100% -> 0% */

    /* 4. Map directly to Modbus Holding Registers or safety trip relay: */
    if (result.condition == AC_STATE_CRITICAL_FAULT) {
        plc_trigger_bearing_alarm_relay(); /* Autonomous machine protection */
    }
}
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